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Reseach Article

VLSI Design, Implementation and Verification of Scalable FFT Processor

Published on July 2018 by Mohammed Irfan M, Naseer Uddin
National Conference on Electronics, Signals and Communication
Foundation of Computer Science USA
NCESC2017 - Number 3
July 2018
Authors: Mohammed Irfan M, Naseer Uddin
5be98c6b-9897-48f4-bf26-f9e40eaf2cef

Mohammed Irfan M, Naseer Uddin . VLSI Design, Implementation and Verification of Scalable FFT Processor. National Conference on Electronics, Signals and Communication. NCESC2017, 3 (July 2018), 15-19.

@article{
author = { Mohammed Irfan M, Naseer Uddin },
title = { VLSI Design, Implementation and Verification of Scalable FFT Processor },
journal = { National Conference on Electronics, Signals and Communication },
issue_date = { July 2018 },
volume = { NCESC2017 },
number = { 3 },
month = { July },
year = { 2018 },
issn = 0975-8887,
pages = { 15-19 },
numpages = 5,
url = { /proceedings/ncesc2017/number3/29621-7104/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Electronics, Signals and Communication
%A Mohammed Irfan M
%A Naseer Uddin
%T VLSI Design, Implementation and Verification of Scalable FFT Processor
%J National Conference on Electronics, Signals and Communication
%@ 0975-8887
%V NCESC2017
%N 3
%P 15-19
%D 2018
%I International Journal of Computer Applications
Abstract

This paper presents designand implementation of a Pipelined FFT Architecture using Verilog HDL. The Pipelined Architectureis implemented using RS2DF(Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement and was programmed on Spartan 3AN FPGA. Simulations and Synthesis are carried using Modelsim and Xilinx ISE. The Verilog Simulations resultsare compared with Inbuilt MATLAB FFT Core for verification of the design. The Speed achieved for this Core is 87. 15 MHz

References
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Index Terms

Computer Science
Information Sciences

Keywords

Fft Spartan 3 saclable Architectures fpga dft