This paper presents designand implementation of a Pipelined FFT Architecture using Verilog HDL. The Pipelined Architectureis implemented using RS2DF(Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement and was programmed on Spartan 3AN FPGA. Simulations and Synthesis are carried using Modelsim and Xilinx ISE. The Verilog Simulations resultsare compared with Inbuilt MATLAB FFT Core for verification of the design. The Speed achieved for this Core is 87. 15 MHz

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Fft Spartan 3 saclable Architectures fpga dft