In this paper, an Ultra-low power 10-bit 200kS/s Successive Approximation Register (SAR) Analog-to-Digital converter is presented. A Split-array charge distribution capacitive DAC is proposed. Spectre simulation results of single-ended 10-bit 200kS/s for supply voltage 1. 8V SAR-ADC in a 0. 18µm CMOS technology employing the proposed architecture show that the SAR ADC consumes 1. 502uW and ADC achieves SNDR of 57. 4dB. The ENOB 9. 24 resulting in a figure of merit (FOM) of 160fJ/conversion-step.

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Successive Approximation Register (sar) Low Power Analog-to-digital Converter (adc) Low Supply Voltage Dac Biomedical Applications