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Modified Double-Edge Triggered Clock Branch Sharing Architecture for Ultra Low Power Design
| International Conference on Microelectronics, Circuits and Systems |
| Foundation of Computer Science USA |
| MICRO - Number 1 |
| October 2014 |
| Authors: Komal Priyadarshini, Srinibasa Padhy |
| 25d5fa11-e2e9-413a-b59d-f2fce95f5811 |
Komal Priyadarshini, Srinibasa Padhy . Modified Double-Edge Triggered Clock Branch Sharing Architecture for Ultra Low Power Design. International Conference on Microelectronics, Circuits and Systems. MICRO, 1 (October 2014), 24-27.
Abstract
Power consumption plays an essential role in VLSI design. Earlier, the VLSI designers were more concentrated on performance and area, but, gradually, low power consumption became one of the most important factors in VLSI design. Increasing demand and growth of portable devices have increased the demand of power efficient VLSI circuits. In this paper, various conventional low power designs are analyzed and a low power double-edge triggered flip-flop using clock branch sharing technique along with MTCMOS and Voltage Scaling technique has been proposed. All the simulations have been carried out using Cadence EDA tools in 0. 18 µm technology at room temperature. The power consumption has reduced significantly as compared to earlier techniques.
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