In The Network on chip (NoC) is an approach to designing the communication subsystem between IP cores in System on Chip (SoC). Network on chip provides an attractive alternative solution to traditional bus based interconnection scheme. NoC architectural design has ability by which various IP cores communicate with one another through router & switching mechanism. The switching mechanism plays a vital role to move the data from an input channel and place it on an output channel. Virtual cut through (VCT) and wormhole (WH) switching techniques are widely used in NoC architecture. In this paper, virtual cut through switching technique has been proposed for Network on chip architecture and its performance is analyzed using the parameters such as latency & power. In this paper we discuss the designing and implementation of VCT router for four IP cores or nodes. The simulation of VCT system is done in Modelsim-SE as a simulation & debugging tool. The design is synthesized in Xilinx ISE 9.1i for the packet size of 16 bits (0-15) on the platform of family automotive spartan2 for device-XC2S200, PQG208 package and speed -5.

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NoC architecture Virtual cut through algorithm Latency