CFP last date
20 January 2025
Reseach Article

Comparative Study of Technology in Semiconductor Memories-A Review

Published on February 2017 by Aman Kumar, Bobbinpreet Kaur
National Conference on Latest Initiatives and Innovations in Communication and Electronics
Foundation of Computer Science USA
IICE2016 - Number 1
February 2017
Authors: Aman Kumar, Bobbinpreet Kaur
2ad99eb4-3067-4f95-9386-0d4db2453092

Aman Kumar, Bobbinpreet Kaur . Comparative Study of Technology in Semiconductor Memories-A Review. National Conference on Latest Initiatives and Innovations in Communication and Electronics. IICE2016, 1 (February 2017), 21-25.

@article{
author = { Aman Kumar, Bobbinpreet Kaur },
title = { Comparative Study of Technology in Semiconductor Memories-A Review },
journal = { National Conference on Latest Initiatives and Innovations in Communication and Electronics },
issue_date = { February 2017 },
volume = { IICE2016 },
number = { 1 },
month = { February },
year = { 2017 },
issn = 0975-8887,
pages = { 21-25 },
numpages = 5,
url = { /proceedings/iice2016/number1/26951-1669/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Latest Initiatives and Innovations in Communication and Electronics
%A Aman Kumar
%A Bobbinpreet Kaur
%T Comparative Study of Technology in Semiconductor Memories-A Review
%J National Conference on Latest Initiatives and Innovations in Communication and Electronics
%@ 0975-8887
%V IICE2016
%N 1
%P 21-25
%D 2017
%I International Journal of Computer Applications
Abstract

In this paper we will present a review on the development of semiconductor Memories through the most recent decade. Starting demands of low power devices is extending therefore; this is the reason for scaling of CMOS advancement. In view of the scaling, size of the chip diminishments and number of transistor in structure on chip increases. Generally the amount of transistors utilized as a piece of chip to store data so, in future the need of low power memories is growing. The extended enthusiasm for mobile phones has incited amazing examination attempts in the setup and progression of low power circuits. Memories are the critical section in present day for automated systems, for instance, chip and Digital Signal Processors (DSPs) that are utilized as a piece of mobile phones. This paper will give a comparison of SRAM memories cell on the basis of their architecture.

References
  1. Jawar Singh, Saraju P. Mohanty, and Dhiraj K. Pradhan Robust SRAM Designs and Analysis" Springer Science+Business Media New York, 2013.
  2. Moore, G. : Cramming more components onto integrated circuits. Electronics 38(8), 534–539 (1965).
  3. Dennard, R. H. : Field-effect transistor memory. US
  4. Patent No. 3387286 (1968)
  5. Cragon, H. G. : Memory Systems and Pipelined Processors, Chapter 1. Jones and Barlett,Sudbury (1996
  6. Hennessy, J. L. , Patterson, D. : Computer Architecture: A Quantitative Approach, Chapter 5. Morgan Kaufman, San Francisco (2006)
  7. ITRS: International technology road map for semiconductors, test and test equipments. (2006)
  8. Carlson, I. , Andersson, S. , Natarajan, S. , Alvandpour, A. : A high density, low leakage,5T SRAM for embedded caches. In: Proceeding of the 30th European Solid-State CircuitsConference, ESSCIRC 2004, Leuven, pp. 215–218 (2004)
  9. Kawaguchi, H. , Kanda, K. , Nose, K. , Hattori, S. , Dwi, D. , Antono, D. , Yamada, D. ,Miyazaki, T. , Inagaki, K. , Hiramoto, T. , Sakurai, T. : A 0. 5 v, 400mhz, v00-hopping processor with zero-vth fd-soi technology. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers. ISSCC, 2003, vol. 1, pp. 106–481 (2003).
  10. Lee, S. , Sakurai, T. : Run-time voltage hopping for low-power real-time systems. In: Proceedings of the 37th Design Automation Conference 2000, Los Angeles, pp. 806–809 (2000)
  11. Wang, A. , Chandrakasan, A. : A 180mv FFT processor using sub-threshold circuit techniques. In: Proceedings of the IEEE ISSCC Dig. Tech. Papers, pp. 229–293 (2004).
  12. Wang, A. , Chandrakasan, A. : A 180-mv subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid-State Circuit 40(1), 310–319 (2005)
  13. Naveen Verma,"Ultra-Low-Power SRAM Design In High Variability
  14. Advanced CMOS," May 2009.
  15. Anurag Dandotiya and Amit S. Rajput ," SNM Analysis of 6T SRAM at 32NM and 45NM Technique ," IJCA, vol. 98, no. 7, July 2014.
  16. Ashok K. Sharma, Semiconductor Memories: Technology, Testing and Reliability, IEEE Press, New York, 1997.
  17. Jinshen Yang, Li Chen,"A New Loadless 4 Transistor SRAM Cell with a 0. 18 µm CMOS Technology". Canadian Conference of Electrical and Computer Engineering, CCECE 2007, pp. 538-541, Apr 2007
  18. Andrei Pavlov, Manoj Sachdev. "CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test". Springer, 2008, pp. 13-77
Index Terms

Computer Science
Information Sciences

Keywords

Sram Cell Low Power Noise Margin Leakage Current