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Reseach Article

Performance Optimization of CP-PLL for SoC Applications

Published on May 2015 by B.k.mishra, Sandhya Save, Jalpaben Pandya
International Conference and Workshop on Emerging Trends in Technology
Foundation of Computer Science USA
ICWET2015 - Number 2
May 2015
Authors: B.k.mishra, Sandhya Save, Jalpaben Pandya
5efe0e29-1238-4686-8aba-d53aab27fd44

B.k.mishra, Sandhya Save, Jalpaben Pandya . Performance Optimization of CP-PLL for SoC Applications. International Conference and Workshop on Emerging Trends in Technology. ICWET2015, 2 (May 2015), 1-6.

@article{
author = { B.k.mishra, Sandhya Save, Jalpaben Pandya },
title = { Performance Optimization of CP-PLL for SoC Applications },
journal = { International Conference and Workshop on Emerging Trends in Technology },
issue_date = { May 2015 },
volume = { ICWET2015 },
number = { 2 },
month = { May },
year = { 2015 },
issn = 0975-8887,
pages = { 1-6 },
numpages = 6,
url = { /proceedings/icwet2015/number2/20936-5019/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology
%A B.k.mishra
%A Sandhya Save
%A Jalpaben Pandya
%T Performance Optimization of CP-PLL for SoC Applications
%J International Conference and Workshop on Emerging Trends in Technology
%@ 0975-8887
%V ICWET2015
%N 2
%P 1-6
%D 2015
%I International Journal of Computer Applications
Abstract

Phase locked loops (PLLs) are integral parts of communication devices used in various applications such as frequency synthesizer, clock recovery circuits, synchronization for digital communications, carrier phase, frequency tracking, etc. The non-ideal effects in PLL such as jitter, phase noise, reference spurs, phase error, etc. influence the PLL performance which significantly affects the overall system. For example, a 10% performance degradation of PLL leads to approximately 20% performance degradation of frequency synthesizers. In conventional CMOS charge pump circuit, phase error is caused due to leakage current, timing mismatch and current mismatch. The phase error due to current mismatch is more significant as compared to phase error due to timing mismatch and leakage current. Thus, in this work, two charge pump circuits with minimum area are designed in Matlab Simulink environment to reduce current mismatch. The designed charge pump using basic current mirror is compared with the ideal current mirror. Simulated results show that current mismatch and phase error for basic current mirror are approximately 12. 19 % and 0. 3480 rad. respectively. This set up can be easily utilized to design various charge pump to achieve minimum current mismatch for SoC applications.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Charge Pump Current Mismatch Current Mirror Design And Performance Of Charge Pump.