Adders are the most important components in digital design which not only perform addition operations, but also useful in calculating many other functions such as subtraction, multiplication and division. Different types of adders are frequently required in VLSI technology according to the requirement in processors to ASICs. In recent research we have found that Complementary Pass transistor Logic (CPL) is much more power-efficient than complementary CMOS. This paper describes the comparative performance of 1-bit CMOS (Complementary MOSFET) full adder,Transmission gate full adder, CPL(Complementary Pass Transistor Logic) full adder and Domino logic full adder, designed using TANNER EDA, using 180nm technology with different CMOS logic design styles. For a particular aspect ratio it is reported that different parameters like Dynamic and Static Power consumption and total propagation delay is less for Transmission gate Full adder.

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1-bit Cmos Full Adder Cpl Full Adder Transmission Gate Full Adder domino Logic Full Adder Cmos Logic Design Styles