An attempt has been made to reduce area requirement while improving electrical characteristics during very large scale integration (VLSI) design. The area can be reduced by designing a layout without diffusion breaks. In this paper, a method is proposed that provides more compact layout without breaks in diffusion with minimal metal pattern, less contacts and low parasitic capacitance. A novel approach towards constructing Euler’s path on complementary metal oxide semiconductor (CMOS) circuit is also discussed

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Euler’s path Optimal layout Metal pattern Diffusion breaks