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Spartan-II FPGA Implementation of 14 Bit, 20msamples/S, 85 Mw Successive Approximation ADC Suitable For RF Applications
| International Conference and Workshop on Emerging Trends in Technology |
| Foundation of Computer Science USA |
| ICWET - Number 6 |
| None 2011 |
| Authors: Rajendra D. Kanphade, Santosh B. Patil, Arum. M. Patokar, Devesh D. Nawgaje |
| 3d749af1-b788-4f0d-b8d9-cb569a33f959 |
Rajendra D. Kanphade, Santosh B. Patil, Arum. M. Patokar, Devesh D. Nawgaje . Spartan-II FPGA Implementation of 14 Bit, 20msamples/S, 85 Mw Successive Approximation ADC Suitable For RF Applications. International Conference and Workshop on Emerging Trends in Technology. ICWET, 6 (None 2011), 7-11.
Abstract
The complexity of the circuits design is growing rapidly with the increasing demand of electronics products in the market. The time available to design a product is shrinking because of competitive pressures. Considerable amount of money get spend in developing an electronics design. FPGA environment is the best solution to address all such issues. In this work FPGA, Matlab, and ISE 9.1i such low cost tools are used to design 14 bit, 20 MSamples/s, 85 mW successive approximation analog-to-digital converter (ADC) suitable for RF applications. Matlab’s Simulink is used to generate VeriLog code for ADC. The design is simulated and synthesized using Xilinx’s ISE 9.1i and finally results are tested on Xilinx’s Spartan II FPGA.
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