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Reseach Article

FPGA Implementation of FFT Using VEDIC Algorithm

Published on None 2011 by Feba D Benny, R Jegan
International Conference on VLSI, Communication & Instrumentation
Foundation of Computer Science USA
ICVCI - Number 9
None 2011
Authors: Feba D Benny, R Jegan

Feba D Benny, R Jegan . FPGA Implementation of FFT Using VEDIC Algorithm. International Conference on VLSI, Communication & Instrumentation. ICVCI, 9 (None 2011), 7-9.

author = { Feba D Benny, R Jegan },
title = { FPGA Implementation of FFT Using VEDIC Algorithm },
journal = { International Conference on VLSI, Communication & Instrumentation },
issue_date = { None 2011 },
volume = { ICVCI },
number = { 9 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 7-9 },
numpages = 3,
url = { /proceedings/icvci/number9/2691-1372/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Proceeding Article
%1 International Conference on VLSI, Communication & Instrumentation
%A Feba D Benny
%A R Jegan
%T FPGA Implementation of FFT Using VEDIC Algorithm
%J International Conference on VLSI, Communication & Instrumentation
%@ 0975-8887
%N 9
%P 7-9
%D 2011
%I International Journal of Computer Applications

Many digital signals processing operation requires several multiplication and for the same we need very fast multiplier for a wide range of requirements for hardware and speed. This paper presents a FFT using for fast and area efficient digital multiplier based on Vedic algorithm. Digital multipliers are the core components of all the digital signal processors (DSPs) and the speed of the DSP is largely determined by the speed of its multipliers. Fast Fourier Transform (FFT) plays an important role in many signal and image processing, data analyzing for vibration sensors, frequency measurement of earthquakes and telecommunication systems such as WiMax technology which presents both wide bandwidth and wireless solutions.

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Index Terms

Computer Science
Information Sciences


Urdhva Triyakbhyam VHDL FFT