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Modeling and Design of Delta-Sigma Analog-To-Digital Converter In 0.18 �M CMOS Process for Audio Applications
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 7 |
| None 2011 |
| Authors: Neetha John |
| 32d36fa2-117d-4757-ab54-6424759bcad9 |
Neetha John . Modeling and Design of Delta-Sigma Analog-To-Digital Converter In 0.18 �M CMOS Process for Audio Applications. International Conference on VLSI, Communication & Instrumentation. ICVCI, 7 (None 2011), 29-34.
Abstract
In this work, the modeling and design of a 10 bit first order delta-sigma analog-to-digital converter in 0.18 μm CMOS process for audio applications will be described. The peak signal-to-noise ratio (SNR) simulated using Matlab program for a 1 KHz sine wave is 78 dB which corresponds to a resolution of 12 bits. The design and analysis of delta-sigma adc was done in the Cadence® custom IC design tool. The transistor level implementation of delta-sigma ADC was done in Cadence.
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