A programmable FPGA based implementation of ahigh frequency All Digital Phase Locked Loop (ADPLL) based clock generator is presented. The novelty of the design lies in its pipelined loop filter for improving the maximum trackedoutput frequencyup to 70MHz. The whole implementation of ADPLL consumes very low dynamic power of 32mW at highest frequency.The digital controlled oscillator (DCO) generates a clock signal with high frequency. The presented ADPLL has fast acquisition and large pull in range for output frequenciesranging from 10Mhz to 70 Mhz. Loop filter is designed to support high speed operation. The whole design including DCO has been done in synthesizable Verilog. It does not contain any library specific cells. The presented design has been implemented in a xc3s400a-4fg320 Xylinx Spartan FPGA. The maximum lock in time for the ADPLL is39 clock cycles.

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All Digital Phase Locked Loop Phase Locked Loop FPGA high speed design lock-in-time