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Design and Implementation of ALU Using Redundant Binary Signed Digit
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 5 |
| None 2011 |
| Authors: Suma T. Hegde, Dr. Siva Yellampalli, Nandeesh R |
| e5611cd9-9c1c-4d52-8539-bf9300fa7e77 |
Suma T. Hegde, Dr. Siva Yellampalli, Nandeesh R . Design and Implementation of ALU Using Redundant Binary Signed Digit. International Conference on VLSI, Communication & Instrumentation. ICVCI, 5 (None 2011), 30-35.
Abstract
In this paper we present the design of an Arithmetic Logic Unit (ALU) based on Redundant Binary signed Digit (RBSD) Number System. A redundant binary representation is a numeral system that uses more bits than needed to represent a single binary digit because of which most numbers have several representations. This unique feature of RBSD number system allows addition without using a typical carry. The RBSD ALU is designed using VHDL and its RTL view is generated by its FPGA implementation. The FPGA implementation is done in Xilinx ISE environment.
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