The project aims to design a UART and the design is needed to be synthesized and verified to carry out physical design activity. For this, synthesis is needed to be carried out with Synopsys DC 2010.13 tool and develop resultant constraints like clock, multi path, false path etc., to meet the timing. The generated net list has to be verified by using Synopsys VCS 2010.10 tool.

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UART Synthesis Gate Level Simulation Synopsys DC Synopsys VCS