In 3G mobile terminals the Viterbi decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. In this paper, to reduce the power consumption, and to increase the speed, an asynchronous technique that is delay insensitive null convention logic (NCL) for Viterbi decoder using dual rail signal is proposed. NCL reduces the dynamic power consumption in terms of reducing the switching activity and also it reduces the glitch power significantly, thereby achieving the lower power. The Viterbi decoder consists of branch metric unit, add compare and select unit and the survivor path memory unit. It is designed in circuit level using null convention logic and simulated using tanner tool in 1.25µm technology 3v vdd and a frequency of 2GHz. The simulation results shows the power consumption of the Viterbi decoder using NCL is 36.14mw, delay of the Viterbi decoder is 6.150ns and the number of transistors required to design the Viterbi decoder is 2058. The Viterbi decoder designed using the null convention logic provides 26% of lower power consumption comparing with that of the CMOS logic.

1. Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, 2005. Design of a Power-Reduction Viterbi Decoder for WLAN Applications, IEEE Transactions on Circuits and System-I: regular papers, 52(6), 321-328G.
2. Irfan Habib, Ozgun Paker, and Sergei Sawitzki,2009, Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation,IEEE transactions on very large scale integration (VLSI) systems, 3,1- 14. a0 a1 b0 b1 clk0 clk1 VDout0 VDout1
3. Jiann S. Yuanand Weidong Kuang, 2004, Teaching Asynchronous Design in Digital Integrated Circuits, IEEE transactions on education,47(3),397-404
4. Injin He, Zhongfeng Wang, Zhiqiang Cui, and Li Li, 2009, Towards an Optimal Trade-off of Viterbi Decoder Design, IEEE conferecne,3030-3033
5. Joshi M.V., Gosavi S., Jegadeesan V., Basu A., Jaiswal S., Al-Assadi W.K. and Smith S.C. 2007, NCL Implementation of Dual-Rail 2s Complement 8×8 Booth2 Multiplier using Static and Semi-Static Primitives, IEEE region 5 Technical Conference, April 20-21, Fayetteville,59- 64.
6. Jun Jin Kong, Keshhab K Parhi., 2004 Low-Latency Architectures for High-Throughput Rate Viterbi Decoder, IEEE Transactions on VLSI System, 12(6), 642-651.
7. Meilana Siswanto1, Masuri Othman, Edmond Zahedi,2006 VLSI Implementation of 1/2 Viterbi Decoder for IEEE P802.15-3a UWB Communication, IEEE ICSE2006 Proc., Kuala Lumpur, Malaysia,666 – 670.
8. Qing Li, Xuan-zhong Li, Han-hong Jiang and Wen-hao He 2008, A High-Speed Viterbi Decoder, Fourth International Conference on Natural Computation IEEE.,p.p. 313-316.
9. Yao Gang, Ahmet T., Erdogan, and Tughrul Arslan, 2006, An Efficient Pre- Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications,IEEE Transactions on Circuits and Systems-I: regular papers, 53(9),423-432
10. Yun-Ching Tang, Do-Chen Hu, Weiyi Wei, Wen-Chung Lin and Hongchin Lin , 2009. A Memory-Efficient Architecture for Low Latency Viterbi Decoders, IEEE.335-338
11. Ajay Dholakia, 1994. Introduction to Convolutional Codes with Applications. Kluwer Academic Publishers. G. Forney, 1973. The Viterbi Algorithm, Proceedings of the IEEE, 61(3),268-278.
12. Dalia A., El-Dib and Elmasry M.I. 2004. Modified Register-Exchange Viterbi Decoder for Low-Power Wireless Communications, IEEE Transactions on Circuits and Systems I, ,51(2), 371- 378.
13. Lang L, Tsui C.Y and Cheng R.S.1997. Low power soft output Viterbi decoder scheme for turbo code decoding, IEEE Conference-Paper, ISCAS „97,New York, USA, 24, 1369-1372

Viterbi Null conventional logic tanner low power high speed