With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication requirements of MPSoCs made of hundreds of cores will not be feasible using a single shared bus or a hierarchy of buses due to their poor scalability with system size, their shared bandwidth between all the attached cores and the energy efficiency requirements of final products[7]. To overcome these problems of scalability and complexity, Networks-On-Chip (NoCs) have been proposed as a promising replacement to eliminate many of the overheads of buses and MPSoCs connected by means of general-purpose communication architectures. In this article we present NoC-based solutions for digital camera to improve the connectivity. The objective of this article is to design, develop and test the TCP/IP offload Engine (TOE).The scope of this article is to design for prototype using Xilinx Virtex-II series FPGA. The final product will be TOE - SoC ASIC. The basic function of the TOE is to provide the network connectivity to the Digital Still Camera. This MPSoCs illustrate the potential benefits of competitive application-specific NoCs.

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Network-on-Chip System-on-Chip Design Automation Digital camera TOE