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High Speed Interconnects - 3GIO Topology
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 18 |
| None 2011 |
| Authors: Rekha Subash, Marie Kottayil James, Rizwana Akbar |
| 38d089de-2143-44d1-85a5-b01e15333d79 |
Rekha Subash, Marie Kottayil James, Rizwana Akbar . High Speed Interconnects - 3GIO Topology. International Conference on VLSI, Communication & Instrumentation. ICVCI, 18 (None 2011), 25-30.
Abstract
Third Generation IO (3GIO) will serve as a general purpose I/O interconnects for a wide variety of future computing platforms. Key PCI attributes, such as its usage model and software interfaces are maintained whereas its bandwidth-limiting, parallel bus implementation is replaced by a long-life, fully-serial interface. A split-transaction protocol is implemented with attributed packets that are prioritized and optimally delivered to their target. The 3GIO definition will comprehend a variety of form factors to support smooth integration with PCI and to enable new system form factors. 3GIO will provide industry leading performance and price/performance.
References
- PCI Express System Architecture - Ravi Budruk, Don Anderson, Tom Shanley
- PCI Express® 2.0 Base Specification Revision 0.9
- HyperTransport™ System Architecture -Don Anderson, Jay Trodden
- RapidIO™ Interconnect Specification, Rev. 2.1
- Creating a Third Generation I/O Interconnect -Ajay V Bhatt, Intel Corporation.
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