Along with the progress of VLSI technology delay buffers plays an increasingly critical role on affecting the circuit design and performance. This paper presents the design of a low power buffer. A gated clock ring counter is used to access the memory. The ring counter uses Double edge triggered flip flops instead of traditional flip flops to half the operating frequency. Also combinational elements are used in the control logic for generating the clock gating signals to avoid the increasing loading of the global clock signal. A gated driver clock tree is then applied to further reduce the activity along the clock distribution network. The gated driver tree technique is also used in the input and output ports of the memory to decrease their loading. The proposed delay buffer consumes less power when compared to the conventional delay buffers.

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C-element gated driver DET flip flop ring counter