The week's pick
Reseach Article
Simulation and Design of Two Full Adder Cells in Subthreshold Region by Various CMOS Technologies and Compare Together
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 18 |
| None 2011 |
| Authors: Manijeh Alizadeh, Behjat Forouzandeh, Reza Sabbaghi-nadooshan |
| e4b0bb34-aacf-49b3-a006-44dfbda650e2 |
Manijeh Alizadeh, Behjat Forouzandeh, Reza Sabbaghi-nadooshan . Simulation and Design of Two Full Adder Cells in Subthreshold Region by Various CMOS Technologies and Compare Together. International Conference on VLSI, Communication & Instrumentation. ICVCI, 18 (None 2011), 6-11.
Abstract
This paper presents two new 1-bit full adder cells operating in subthreshold region with 65nm, 90nm and 0.18um technologies. Circuits designed in this region usually consume less power. Inverse Majority Gate (IMG) together with NAND/NOR were used as the main computational building blocks. A modification was done to optimize W/L ratios with different supply voltages. We used W/L ratios for all the PMOS transistors 1.5 times the ratio of W/L for all NMOS transistors. Compared with a previously reported minority-3 based full adder; the results involve better performance in terms of power, delay, and PDP.
References
- Aunet, S., Oelmann, B., Abdalla, S. and Berg, Y. 2004. “Reconfigurable Sub-threshold CMOS Perceptron,” International Joint Conference on Neural Networks, IJCNN, pp. 1983-1988.
- Aunet, S. 2007. Kretselement U.S. Patent 7,288,968.
- Granhaug, K. and Aunet, S. 2006. “Six Subthreshold Full Adder Cells characterized in 90 nm CMOS technology,” DDECS, pp. 27-32.
- Aunet, S. and Beiu, V. 2005. “Ultra low power fault tolerant neural inspired CMOS logic,” in Proc. IEEE Int. Joint Conf. Neural Network, pp. 2843-2848.
- Aunet, S. 2003. Kretselement, Norwegian patent application, no. 20035537, Leiv Eiriksson Nyskapning, Trondheim, Norway.
- Moalemi, V. and Afzali-Kusha, A. 2007. “Sub Threshold 1 Bit Full Adder Cells in Sub100 nm Technology,” IEEE Computer Society Annual Symposium on VLSI, pp. 514- 515.
- Soeleman, H., Roy, K. and. Paul,B.C. 2001. “Robust subthreshold logic for ultra-low power operation,” IEEE Trans. VLSI Syst.
- Aunet, S., Oelmann, B.,Andreas,P. and Berg Y. 2008. “Real- Time Reconfigurable Subthreshold CMOS Perceptron,”IEEE Transaction 0n Neural Network, Vol.19, No.4, pp. 645-657, APRIL 2008.
- Razavi, B. Design of Analog CMOS Integrated Circuits.
- Navi, K., Moaiyeri, M.H., Faghih Mirzaee, R., Hashemipour, O. and Mazloom Nezhad, B. 2009. “Two novel lowpower full adders based on majority-not gates”, Elsevier, Microele-ctronics Journal Journal, Vol. 40, Issue. 1, pp. 126- 130.
- Shams, A.M. and Bayoumi, M.A. 2000. “A Novel High- Performance CMOS 1-bit Full Adder Cell,”IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, Vol. 47, No. 5, pp. 478-481, May 2000.
- Shams, A.M., Darwish, T.K. and Bayoumi, M.A. 2002. “Perfor- mance Analysis of Low-Power 1-Bit CMOS Full Adder Cells,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 1, pp. 20-29, Feb. 2002.
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