CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

Effect of Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations

Published on None 2011 by K.K.Nagarajan, N.Vinodhkumar, Dr.R.Srinivasan
journal_cover_thumbnail

International Conference on VLSI, Communication & Instrumentation
Foundation of Computer Science USA
ICVCI - Number 16
None 2011
Authors: K.K.Nagarajan, N.Vinodhkumar, Dr.R.Srinivasan
e7458f7a-b107-4801-84fb-7a29a02176bc

K.K.Nagarajan, N.Vinodhkumar, Dr.R.Srinivasan . Effect of Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations. International Conference on VLSI, Communication & Instrumentation. ICVCI, 16 (None 2011), 6-10.

@article{
author = { K.K.Nagarajan, N.Vinodhkumar, Dr.R.Srinivasan },
title = { Effect of Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations },
journal = { International Conference on VLSI, Communication & Instrumentation },
issue_date = { None 2011 },
volume = { ICVCI },
number = { 16 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 6-10 },
numpages = 5,
url = { /proceedings/icvci/number16/2747-1587/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on VLSI, Communication & Instrumentation
%A K.K.Nagarajan
%A N.Vinodhkumar
%A Dr.R.Srinivasan
%T Effect of Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations
%J International Conference on VLSI, Communication & Instrumentation
%@ 0975-8887
%V ICVCI
%N 16
%P 6-10
%D 2011
%I International Journal of Computer Applications
Abstract

The effect of gate – drain/source underlap ( Lun ) on a narrow band LNA performance has been studied , in 30 nm FinFET using device and mixed mode simulations. Studies are done by maintaining and not maintaining the leakage current (Ioff) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain and noise-figure have been used as performance metrics. To get the better noise performance and gain, Lun in the range of 3-5nm is recommended.

References
  1. Qiuting Huang, Francesco Piazza, and Tatsuya Ohgura. The impact of scaling down to deep sub-micron on CMOS RF circuits. IEEE journal of solid state circuits, 33(7): pp 1023-1036, 1998.
  2. Hau-Yiu Tsui and jack Lau. SPICE simulation and tradeoffs of CMOS LNA performance with source-degeneration inductor. IEEE Trans. On Circuits and Systems-II: Analog and Digital Signal Processing, 47(1): 62-65, Jan 2000.
  3. Bernhard SCHMITHUSEN, Andreas SCHENK, and wolfgang FICHTNER. Simulation of noise in semiconductor devices with dessis-ISE using the direct impedance field method. Technical report, 2000/08, June 2000.
  4. Andreas SCHENK, Bernhard SCHMITHUSEN, Andreas WETTSTEIN, Axel ERLEBACH, Simon BRUGGER, Fabian.M.BUFLER, Thomas FEUDEL, and wolfgang FICHTNER. Simulation of RF noise in MOSFETs using different transport models. IEICE Trans. Electron., E86-C(3):481-489, March 2003.
  5. Yuhua Cheng and Mishel Matloubian. High frequency characterization of gate resistance in RF MOSFETs. IEEE Electron Device Letters, 22(2): 28-30, Feb 2001.
  6. Fathipour Morteza, Nematian Hamed, Kohani Fatemeh. The impact of structural parameters on the electrical characteristics of nano scale DG-SOI MOSFETs in subthreshold region. 4th International Conference: Sciences of Electronic, Technologies of Information and Telecommunications (SETIT 2007), Tunisia, March 25-29, 2007.
  7. R.Shrivastava and K.Fitzpartick. A simple model for the overlap capacitance of a VLSI MOS device. IEEE Trans. Electron Devices, Vol.ED-29, pp.1870-1875, 1982.
  8. R.Srinivasan and Navakanta Bhat, Optimisation of Gate to Drain/Source overlap on noise in 90nm NMOSFETs for Low Noise Amplifier performance, Journal of low power electronics, American Scientific Publishers, Vol 4,No-2,2008, PP 240-246.
Index Terms

Computer Science
Information Sciences

Keywords

FinFET LNA TCAD Underlap