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Reseach Article
Implementation of Vedic Multiplier for Digital Signal Processing
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 16 |
| None 2011 |
| Authors: Prakash Narchi, Siddalingesh S. Kerur, Jayashree C. Nidagundi, Harish M Kittur, Girish V A |
| 18eb7e84-ae21-4e84-b849-2e3df991aa61 |
Prakash Narchi, Siddalingesh S. Kerur, Jayashree C. Nidagundi, Harish M Kittur, Girish V A . Implementation of Vedic Multiplier for Digital Signal Processing. International Conference on VLSI, Communication & Instrumentation. ICVCI, 16 (None 2011), 1-5.
Abstract
Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms, etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. Among the various methods of multiplication in Vedic mathematics, Urdhava tiryakbhyam is discussed in detail. Urdhava tiryakbhyam is the general multiplication formula applicable to all cases of multiplication. The coding is done in VHDL (very high speed integrated circuit hardware description language) and synthesis is done using Xilinx ISE series. The combinational delay obtained after the synthesis is compared with normal multiplier. Further, this Vedic multiplier is used in matrix multiplication. This Vedic multiplier can bring great improvement in the DSP performance.
References
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- Harpreet Singh Dhillon and Abhijit Mitra, “A Reduced- Bit Multiplication Algorithm for Digital Arithmetics”, International Journal of Computational and Mathematical Sciences 2;2 © www.waset.org Spring 2008.
- Himanshu Thapliyal and M.B Srinivas, “An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics”, IEEE, 2005.
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