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Implementation of Vedic Multiplier for Digital Signal Processing

Published on None 2011 by Prakash Narchi, Siddalingesh S. Kerur, Jayashree C. Nidagundi, Harish M Kittur, Girish V A
journal_cover_thumbnail

International Conference on VLSI, Communication & Instrumentation
Foundation of Computer Science USA
ICVCI - Number 16
None 2011
Authors: Prakash Narchi, Siddalingesh S. Kerur, Jayashree C. Nidagundi, Harish M Kittur, Girish V A
18eb7e84-ae21-4e84-b849-2e3df991aa61

Prakash Narchi, Siddalingesh S. Kerur, Jayashree C. Nidagundi, Harish M Kittur, Girish V A . Implementation of Vedic Multiplier for Digital Signal Processing. International Conference on VLSI, Communication & Instrumentation. ICVCI, 16 (None 2011), 1-5.

@article{
author = { Prakash Narchi, Siddalingesh S. Kerur, Jayashree C. Nidagundi, Harish M Kittur, Girish V A },
title = { Implementation of Vedic Multiplier for Digital Signal Processing },
journal = { International Conference on VLSI, Communication & Instrumentation },
issue_date = { None 2011 },
volume = { ICVCI },
number = { 16 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 1-5 },
numpages = 5,
url = { /proceedings/icvci/number16/2746-1586/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on VLSI, Communication & Instrumentation
%A Prakash Narchi
%A Siddalingesh S. Kerur
%A Jayashree C. Nidagundi
%A Harish M Kittur
%A Girish V A
%T Implementation of Vedic Multiplier for Digital Signal Processing
%J International Conference on VLSI, Communication & Instrumentation
%@ 0975-8887
%V ICVCI
%N 16
%P 1-5
%D 2011
%I International Journal of Computer Applications
Abstract

Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms, etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. Among the various methods of multiplication in Vedic mathematics, Urdhava tiryakbhyam is discussed in detail. Urdhava tiryakbhyam is the general multiplication formula applicable to all cases of multiplication. The coding is done in VHDL (very high speed integrated circuit hardware description language) and synthesis is done using Xilinx ISE series. The combinational delay obtained after the synthesis is compared with normal multiplier. Further, this Vedic multiplier is used in matrix multiplication. This Vedic multiplier can bring great improvement in the DSP performance.

References
  1. Charles. Roth Jr. “Digital Systems Design using VHDL,” Thomson Brooks/Cole, 7th reprint, 2005.
  2. Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda, Delhi (1965).
  3. H. Thapliyal and M. B. Shrinivas and H. Arbania, “Design and Analysis of a VLSI Based High Performance Low Power Parallel Square Architecture”, Int. Conf. Algo. Math.Comp. Sc., Las Vegas, June 2005, pp. 72-76.
  4. P. D. Chidgupkar and M. T. Karad, “The Implementation of Vedic Algorithms in Digital Signal Processing”, Global J. of Engg. Edu, vol.8, no.2, 2004.
  5. Shamim Akhter,”VHDL Implementation Of Fast NXN Multiplier Based On Vedic Mathematics”, Jaypee Institute of Information Technology University, Noida, 201307 UP, INDIA, 2007 IEEE.
  6. Harpreet Singh Dhillon and Abhijit Mitra, “A Reduced- Bit Multiplication Algorithm for Digital Arithmetics”, International Journal of Computational and Mathematical Sciences 2;2 © www.waset.org Spring 2008.
  7. Himanshu Thapliyal and M.B Srinivas, “An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics”, IEEE, 2005.
  8. Himanshu Thapliyal and M.B Srinivas, “VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics”, Center for VLSI and Embedded System Technologies, International Institute of Information Technology Hyderabad-500019, India.
Index Terms

Computer Science
Information Sciences

Keywords

Vedic multiplier Urdhava tiryakbhyam VHDL DSP