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Reseach Article

FPGA Implementation of New Generation Block Cipher

Published on None 2011 by Sita Radhakrishnan, Dhanusha P B, Shyamraj R
journal_cover_thumbnail
International Conference on VLSI, Communication & Instrumentation
Foundation of Computer Science USA
ICVCI - Number 15
None 2011
Authors: Sita Radhakrishnan, Dhanusha P B, Shyamraj R
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Sita Radhakrishnan, Dhanusha P B, Shyamraj R . FPGA Implementation of New Generation Block Cipher. International Conference on VLSI, Communication & Instrumentation. ICVCI, 15 (None 2011), 35-38.

@article{
author = { Sita Radhakrishnan, Dhanusha P B, Shyamraj R },
title = { FPGA Implementation of New Generation Block Cipher },
journal = { International Conference on VLSI, Communication & Instrumentation },
issue_date = { None 2011 },
volume = { ICVCI },
number = { 15 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 35-38 },
numpages = 4,
url = { /proceedings/icvci/number15/2770-1688/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on VLSI, Communication & Instrumentation
%A Sita Radhakrishnan
%A Dhanusha P B
%A Shyamraj R
%T FPGA Implementation of New Generation Block Cipher
%J International Conference on VLSI, Communication & Instrumentation
%@ 0975-8887
%V ICVCI
%N 15
%P 35-38
%D 2011
%I International Journal of Computer Applications
Abstract

The demand for efficient and secure ciphers has given rise to a new generation of block ciphers capable of providing increased protection at lower cost. Among these new algorithms is Twofish, a promising 128-bit block cipher that could soon be chosen by the National Institute of Standards and Technology as the Advanced Encryption Standard, replacing DES at the core of many encryption systems worldwide. In this project, a version of Twofish with 192-bit key length will be implemented using VHDL.

References
  1. ―High-Speed VLSI Architectures for the AES Algorithm‖, Xinmiao Zhang, Student Member, IEEE, and Keshab K. Parhi, Fellow, IEEE- IEEE Trans. On VLSI Systems, VOL. 12, NO. 9, September 2004
  2. C. C. Lu and S. Y. Tseng, ―Integrated design of AES (advanced encryption standard) encrypter and decrypter,‖ in Proc. IEEE Int. Conf. Application Specific Systems, Architectures Processors, 2002, Pp. 277–285.
  3. An FPGA-Based Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists Adam J. Elbirt, W. Yip, B. Chetwynd, and C. Paar-IEEE Trans. On VLSI systems, VOL. 9, NO. 4, August 2001
  4. X. Zhang and K. K. Parhi, ―Implementation approaches for the advanced encryption standard algorithm,‖ IEEE Circuits Syst. Mag., vol. 2, no. 4, pp. 24–46, 2002.
  5. ―A Highly Regular and Scalable AES Hardware Architecture‖ IEEE Trans.on Computers, VOL. 52, NO. 4, April 2003
  6. Fast software encryption, Third International workshop proceedings, Springer-Verlag
  7. Bruce Schneier, John Kelsey, Doug Whiting, David Wagner, Chris Hall, and Niels Ferguson, ―The Twofish Encryption Algorithm‖, Wiley, 1999
  8. H. Kuo and I. Verbauwhede, ―Architectural Optimization for a1.82Gbits/Sec VLSI Implementation of the AES Rijndael Algorithm,‖ Proc. Workshop Cryptographic Hardware and Embedded Systems—CHES 2001, pp. 51-64, 2001.
  9. Baskar J. (1998) ‗A VDHL Premiere‘ Prentice Hall of India, III Edition.
  10. Charlies H. Roth Jr. (1998), ―Digital System Design using VHDL‖, PWS Publishing, Baston Company, II Edition.
  11. William Stallings, ―Cryptography And Network Security: Principles and Practice‖ IVth Edition.
Index Terms

Computer Science
Information Sciences

Keywords

AES DES S BLOCK