The VLSI placement problem is to place objects into a fixed die such that there are no overlaps among objects and some cost metrics (wire length, routability) are optimized. The nature of multiple objects and incremental design process for modern VLSI design demands Advanced Incremental Placement Techniques. Incremental placement changes either the wire length or the Placement Density of an existing placement to optimize one or more design objectives. The difficulty of Incremental Placement lies in that it is hard to optimize one design objective while maintaining the existing optimized design objectives. In this dissertation, three main approaches are used to overcome this problem. The first approach is to perform sensitivity analysis and make smaller changes one step at a time on the most sensitive direction. This approach always changes placement in the direction where a change can result in the highest improvement in design objective. The second approach is to maintain the relative order during Incremental Placement. This is called a „Correct-byconstruction‟ approach. When we move cells while maintaining their relative order, it is implicitly preserve the existing design characteristics. The third approach is to specify maintain other design constraints while optimizing one design objective. This is more direct approach. It needs to formulate design constraints that can be honored by incremental placer. For the first approach, two techniques are available. First technique is „Sensitivity based Netweighting‟. The objective is to maintain both Worst Negative Stack (WNS) and Figure of Merit (FOM), defined as the Total Stack Difference, compared to a certain Threshold for all timing end points. It performs Incremental global placements with the netweights based on comprehensive analysis of the wirelength, Slack on FOM sensitivities to the netweight. The second technique is noise map driven two step incremental placements. The novel noise map is used to estimate the placement impact on coupling noise, which takes into account of Coupling Capacitance, Driver Resistance and Wire resistance. It performs a two step incremental placement i.e., cell inflation and Local refinement, to expand regions with high noise impact in order to reduce Total Noise. The technique for second approach is Diffusion based Placement Migration, which is the smooth movement of the cells in an existing placement to address a variety of post placement design issues. This method simulates a diffusion process where cells move from high concentration area to low concentration area. The application on Placement Legalization shows significant improvements in wirelength and timing as compared to the other commonly used legalization techniques. For the third approach, a technique called First-do-noharm detailed placement is used. It uses set of pin-based timing and electrical constraints to prevent detailed placement techniques from degrading timing or violating electrical constraints while reducing wirelength. This technique will provide better result for detailed placement not only reduces TotalWirelength (TWL), but also significantly improves timing.

1. ISPD 2006 Program, http://www.ispd.cc/program.html
2. http://www.sigda.org/daforum/2006/accepted06/36.html
3. Wayn Wolf: Modern VLSI Design, System-On-Chip Design, III Edition, Pearson Education, Pages 185 – 225 & 359 – 382, 2005
4. Jason Cong, Lei He, Chang-kok Koh and patric, H Madden, Performance optimization of vLSI interconnect and placement.
5. C.C. Chang, J.Cong and X. Yuan, Multi-Level placement for Large-scale, mixed-size IC designs, ln Proc Asis South Pacific Design Atomation Conf., Pages 325-330, 2003.

Optimization Placement Modern VLSI Design Worst Negative Stack (WNS) Figure of Merit (FOM)