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An improved graphical methodology for CMOS Analog Circuit Design
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 12 |
| None 2011 |
| Authors: Bhupendra Vishwakarma, Sudip Sarkar |
| 4566aff4-af31-4267-9efc-6985241c43ad |
Bhupendra Vishwakarma, Sudip Sarkar . An improved graphical methodology for CMOS Analog Circuit Design. International Conference on VLSI, Communication & Instrumentation. ICVCI, 12 (None 2011), 34-37.
Abstract
This tutorial presents a graphical methodology to design basic analog CMOS blocks. We have introduced (gm/Id) Vs. (gds/Id) plot to characterize MOS transistors in different regions. This methodology requires no iterations to achieve desired specifications compared to traditional (gm/Id) method in nanometer scale designs. Using a 45nm CMOS process we have designed Common source, cascode, differential and Telescopic operational amplifiers focusing on their gain requirements. Cadence IC614 Schematic XL, ADE XL and Spectre7.1 have been used for design and simulation purpose.
References
- Behzad Razavi, “Design of Analog CMOS Integrated Circuits” International Edition, McGraw Hill
- Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”
- Paul G. A. Jespers, “The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits”, Springer, 2009.
- S. Chatterjee, K.P. Pun, N. Stanic, Y. Tsividis, P. Kinget, "Analog Circuit Design Techniques at 0.5V", Springer, New York, USA, 2007.
- Denis Flandre, Alberto Viviani, Jean-Paul Eggermont, Bernard Gentinne, and P. G. A. Jespers, “Improved Synthesis of Gain-Boosted Regulated-Cascode CMOS Stages Using Symbolic Analysis and gm/ID Methodology” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 7, JULY 1997
- H. Daoud Dammak, S. Bensalem, S. Zouari, and M. Loulou, “Design of Folded Cascode OTA in Different Regions of Operation Through gm/ID Methodology” International Journal of Electrical Systems Science and Engineering 2008
- Silveira, D. Flandre et P.G.A. Jespers, “A gm/ID based methodology for the design of CMOS analog circuits and application to the synthesis of a SOI micropower OTA”, IEEE J. of Solid State Circuits, vol. 31, n. 9, sept. (1996)
- Fernando Paixao Cortes, Sergio Bampi, “Miller OTA design using a design methodology based on the gm/ID and early voltage characteristics : Design considerations and experimental results”
- Daniel Foty, David Binkley, and Mattias Bucher, “gm/Id – Based MOSFET Modeling and Modern Analog Design”, Presented at MIXDES Wroclaw, Poland 2002
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