A serial-serial hybrid multiplier presented for applications with high data sampling rate (4GHz). In this technique entire partial product matrix requires only n sampling cycles for an n × n multiplication instead of at least 2n cycles in the conventional serial-serial multipliers. The 1’s counter is used to column compress the partial products (PP). It replaces conventional full adders and 5:3 counters with asynchronous 1’s counters so that the critical path is limited to only an AND gate and a D flip-flop (DFF). It reduces the height of the partial product matrix from n to [log2 n] +1. Multiplier dissipates only 21% less power at a sampling rate of 4 GHz compared to conventional wallace tree multiplier, and has only 11% additional delay penalty to complete a multiplication compared to the conventional fully parallel CSA array multiplier. This serial-serial multiplier finds application in system-on–chip.

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System On-Chip partial products serial-serial multiplier data sampling rate array multiplier