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New Efficient 2T AND Gate Design
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 11 |
| None 2011 |
| Authors: Tripti Sharma, K.G.Sharma, Km. Deepmala, B.P.Singh |
| a13ddb40-07b4-4432-a36b-e330b5d52b11 |
Tripti Sharma, K.G.Sharma, Km. Deepmala, B.P.Singh . New Efficient 2T AND Gate Design. International Conference on VLSI, Communication & Instrumentation. ICVCI, 11 (None 2011), 30-33.
Abstract
This paper proposes a new design of 2T AND gate. Performance comparison of proposed gate with existing 2T GDI technique is presented. Different methods have been compared with respect to the number of devices, power consumption, power-delay product, temperature sustainability and noise immunity in order to prove the superiority of proposed design over existing 2T gate design. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm technology.
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