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Reseach Article

New Efficient 2T AND Gate Design

Published on None 2011 by Tripti Sharma, K.G.Sharma, Km. Deepmala, B.P.Singh
International Conference on VLSI, Communication & Instrumentation
Foundation of Computer Science USA
ICVCI - Number 11
None 2011
Authors: Tripti Sharma, K.G.Sharma, Km. Deepmala, B.P.Singh
a13ddb40-07b4-4432-a36b-e330b5d52b11

Tripti Sharma, K.G.Sharma, Km. Deepmala, B.P.Singh . New Efficient 2T AND Gate Design. International Conference on VLSI, Communication & Instrumentation. ICVCI, 11 (None 2011), 30-33.

@article{
author = { Tripti Sharma, K.G.Sharma, Km. Deepmala, B.P.Singh },
title = { New Efficient 2T AND Gate Design },
journal = { International Conference on VLSI, Communication & Instrumentation },
issue_date = { None 2011 },
volume = { ICVCI },
number = { 11 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 30-33 },
numpages = 4,
url = { /proceedings/icvci/number11/2712-1456/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on VLSI, Communication & Instrumentation
%A Tripti Sharma
%A K.G.Sharma
%A Km. Deepmala
%A B.P.Singh
%T New Efficient 2T AND Gate Design
%J International Conference on VLSI, Communication & Instrumentation
%@ 0975-8887
%V ICVCI
%N 11
%P 30-33
%D 2011
%I International Journal of Computer Applications
Abstract

This paper proposes a new design of 2T AND gate. Performance comparison of proposed gate with existing 2T GDI technique is presented. Different methods have been compared with respect to the number of devices, power consumption, power-delay product, temperature sustainability and noise immunity in order to prove the superiority of proposed design over existing 2T gate design. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm technology.

References
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Index Terms

Computer Science
Information Sciences

Keywords

New Efficient 2T Gate Design