In this paper the Design and Verification of High performance PLL is presented and implemented at 180nm CMOS Process Technology. Process and Temperature Compensation Techniques for minimizing the variation of the free-running frequency of Voltage Controlled Oscillator are discussed. Matched up and down currents Charge Pump is designed. 2 types of PFDs are presented with their consequences. Type 1 PFD is designed with more area and zero dead zone which is compared with type 2 PFD which is designed with less area but 0.01n sec dead zone. The PLL is operated at 1.25GHz with power supply of 1.8V.

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charge pump loop filter process voltage temperature (PVT) ring oscillator voltage controlled oscillator