This paper presents a novel architecture of Inter Integrated Circuit (I2C) slave module for embedded processor at protocol level to provide flexibility. The internals of modular description follows higher level of abstraction in Verilog Hardware Description Language (HDL) to provide a technology independent design for Field Programmable Gate Array (FPGA) implementation using Xilinx ISE 12.1. A brief contrast analysis has been carried out from logic synthesis results obtained by targeting the process technologies of 90nm, 65nm, 45nm and 40 nm individually on Xilinx FPGAs. The behavioral model has been simulated to verify the complete functionality of I2C serial transmission protocol through the instantiation of slave module in a top-level stimulus block. One-hot Finite State Machine (FSM) encoding scheme is being adopted for slave transceiver to exhibit the I2C cycle operation. The target device Virtex6: xc6vlx75t-3ff484 offers maximum frequency.

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I2C SDA SCL FPGA FSM One-Hot Encoding