The week's pick
Reseach Article
Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL
| International Conference on Quality Up-gradation in Engineering Science and Technology |
| Foundation of Computer Science USA |
| ICQUEST2016 - Number 2 |
| August 2017 |
| Authors: Bhagyashree. V. Dagamwar, R. N. Mandavgane, D. M. Khatri |
| 9231fe0e-3262-4d44-87f4-c521ec1dd8c6 |
Bhagyashree. V. Dagamwar, R. N. Mandavgane, D. M. Khatri . Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL. International Conference on Quality Up-gradation in Engineering Science and Technology. ICQUEST2016, 2 (August 2017), 12-16.
Abstract
In general, multiplication plays an vital role in the development of processors, DSP applications, image processing etc. So, designing of high speed multiplier is a neccesary choice. In this research, design of 4, 8 and 16-bit multiplier based on vedic mathematics has been presented. These multipliers further will be used in the design of convolutional encoder. Here, Urdhava Tiryakbhyam sutra is used for multiplication. It eliminates unwanted multiplication steps and follows a fast multiplication process and achieves a significantly less computation complexity over its conventional counterparts. All the modules are coded in VHDL and simulation done in Xilinx ISE 14. 5i.
References
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