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A Review on Design a Low Power Flip-Flop Based On a Signal Feed-Through Scheme

Published on October 2015 by Mayur D. Ghatole, and M. A. Gaikwad
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International Conference on Advancements in Engineering and Technology (ICAET 2015)
Foundation of Computer Science USA
ICQUEST2015 - Number 1
October 2015
Authors: Mayur D. Ghatole, and M. A. Gaikwad
296a081c-ab71-4ebc-aa3c-2159c456d33b

Mayur D. Ghatole, and M. A. Gaikwad . A Review on Design a Low Power Flip-Flop Based On a Signal Feed-Through Scheme. International Conference on Advancements in Engineering and Technology (ICAET 2015). ICQUEST2015, 1 (October 2015), 13-16.

@article{
author = { Mayur D. Ghatole, and M. A. Gaikwad },
title = { A Review on Design a Low Power Flip-Flop Based On a Signal Feed-Through Scheme },
journal = { International Conference on Advancements in Engineering and Technology (ICAET 2015) },
issue_date = { October 2015 },
volume = { ICQUEST2015 },
number = { 1 },
month = { October },
year = { 2015 },
issn = 0975-8887,
pages = { 13-16 },
numpages = 4,
url = { /proceedings/icquest2015/number1/22978-2779/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Advancements in Engineering and Technology (ICAET 2015)
%A Mayur D. Ghatole
%A and M. A. Gaikwad
%T A Review on Design a Low Power Flip-Flop Based On a Signal Feed-Through Scheme
%J International Conference on Advancements in Engineering and Technology (ICAET 2015)
%@ 0975-8887
%V ICQUEST2015
%N 1
%P 13-16
%D 2015
%I International Journal of Computer Applications
Abstract

Flip-flops and latches are the most important elements of a design for both a delay and energy point of view. In many electronics design low power consumption is basic need in most of the applications. The energy performance requirements enhance the most designers of next generation system towards the least possible power consumption. The power consumption is basically reduced by scaling of a power supply voltage. Flip flops typically consumes more than 50% of random logic power in the SoC chip, because of redundant transition of internal node. A low power flip flop design featuring pulse triggered structure based on signal feed-through scheme is presented which successfully solves the long discharging path problem in a various pulse triggered flip flop design and achieve a better power performance and better speed. In this paper we have studied all the major techniques to achieve a low power flip flop and presented their comparison.

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Index Terms

Computer Science
Information Sciences

Keywords

Flip-flops Low Power Pulse Triggered Leakage Power Pipelining.