Testing of combinational circuit is crucial important to ensure high level of functionality. As density of digital circuit increases rapidly day by day these increases cost and time to test a particular combinational circuit for testing such circuit we need high quality test vector pattern with minimum number of input combination. In this work, we are designing Automatic test pattern generator (ATPG) D_Algorithm which will generate a minimum number of input pattern to detect fault like stuck-at-0 fault, stuck-at-1 fault, short circuit fault. D_Algorithm has been design by writing practical extraction and report language script to generate VHDL coding which is simulated on Xilinx 9. 1.

1. Luca Mostardini, Luca Bacciarelli, Luca Fanucci, Lorenzo Bertini, Marco Tonarelli, Marco De Marinis, "FPGA –based Low-cost Automatic Test Equipment for digital integrated Circuits," IEEE international workshop on intelligent Data Acquisition and Advanced computing system. Sept 2009
2. F. Kocan, and D. Saab, "Concurrent d-algorithm on reconfigurable hardware, "Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, pp. 152-156, 1999.
3. S. Jamuna and V. K. Agrawal, "VHDL Implementation of BIST Controller," in Proc. Of int. conf. on Advances in Recent Technologies in communication and computing. Pp. 188-190, 2011.
4. E. J. McCluskey and F. W. Clegg, "Fault equivalence in combinational logic networks," IEEE Tran computer vol. C-20, pp. 1286-1293.
5. I. Pomeranz and W. K. Fuchs, "A Diagonistic test generation procedure for combinational circuits based on test elimination," in Proc. IEEE Asian Test Symp, pp. 486-491.
6. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital System testing and testable Design, IEEE press, 1994.
7. T. Kirkland and M. R. Mercer, "A topological search algorithm for ATPG," in proc. DAC-87, pp. 502-508.
8. Joe Dunbar "FPGA Based Design for Accelerated Fault-Testing of Integrated Circuits. " Bucknell University Jan 2010
9. Miron Abeamovici, Melvin A. Breuer, Arthur D. Friedman, "Testing For Single Stuck At Faults" in Digital Systems and Testable Design. IEEE press New York.
10. Michael L. Bushnell, Vishwani D. Agrawal , "Combinational Circuit Test generation" in Essential Of Electronic Testing For Digital Memory and mixed signal VLSI Circuits. Kluwer Academic Publisher New York, Boston, Dordrecht, London, Moscow.
11. P. Ellervee, J. Raik, and V. Tihhomirov, "Fault emulation on FPGA: a feasibility study," In Proceedings of the 21st NORCHIP Conference, Riga, Latvia, pp. 92-95, 2003.
12. V. D. Agrawal, D. H. Baik, Y. C. Kim, and K. K. Saluja, "Exclusive Test and its Applications to Fault Diagnosis," in Proc. 16th International Conf. VLSI Design, Jan. 2003, pp. 143-148.
13. Yu Zhang "Diagnostic Test Pattern Generation and Fault simulation for Stuck-at and transition Faults," a dissertation. August 4, 2012.
14. P. Camurati, A. Lioy, P. Prinetto, and M. S. Reorda, "A Diagnostic Test Pattern Generation Algorithm," in Proc. International Test Conf. , 1990, pp. 52-58.

Atpg (automatic Test Pattern Generator) Fpga (field Programming Gate Arrays) Fate (fpga Based Automatic Test Equipment) Cut (circuit Under Test)