This paper presents an efficient approach that greatly reduces the hardware consumption during the design of FIR filters. Linear phase FIR filters are designed by exploiting the nature of symmetric odd coefficients. The efficient usage of coefficients limits the number of multipliers while simultaneously increasing the number of adders, which does not influence the hardware cost to a greater extent. Parallel processing together with linear phasing is a powerful technique which can be used to increase the throughput of the FIR filter or reduce the power consumption of the FIR filter. Replacement of adders instead of multipliers is advantageous because adders weigh less in cost in terms of its silicon area and also the number of sub filter blocks remains fixed and does not increase along with the length of the FIR filter. By using the combination of fast FIR filtering and area reduction technique, a major reduction of multipliers is done.

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Digital Signal Processing (dsp) - Fir Filter –linear Phase – Parallel Processing – Odd Coefficients.