In this paper, we proposed a low power 1-bit full adder (FA) with 10-transistors and this is used in the design ALU. 16-bit ALUs are designed and compared with the existing design. The proposed design consists of PTL-GDI adder and mux circuits. By using low power 1-bit full adder in the implementation of ALU, the power and area are greatly reduced to more than 50% compared to conventional design and 30% compared to transmission gates. So, the design is attributed as an area efficient and low power ALU. This design does not compromise for the speed as the delay of the full adder is minimized thus the overall delay. The leakage power of the design is also reduced by designing the full adder with less number of power supplies to ground connections. In fact, power considerations have been the ultimate design criteria in special portable applications. For large number of computations, efficient ALU is to be designed for minimum area and low-power without compromising the high speed. The proposed ALU design simulated using tanner version 13 software.

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Gate Transmission Input Pass Transistor Logic 10t Full Adder Mux.