Floorplanning is an essential step in VLSI chip design automation. The main objective of the floorplanning is to find a floorplan such that the cost is minimized. This is achieved by minimizing the chip area and interconnection cost. It determines the performance, size, yield and reliability of VLSI chips. We propose a Memetic Algorithm (MA) for non-slicing and hard module VLSI floorplanning problem. This MA is a hybrid genetic algorithm that uses effective genetic search method to explore the search space and an efficient local search method to exploit information in the search region. The exploration and exploitation are balanced by threshold bias search strategy. MA works better than the existing algorithms and is efficient, faster and cost effective algorithm. A better floorplan with minimal chip area and interconnection cost will be obtained using the MA for non-slicing and hard module VLSI floorplanning problem. MA is mainly used to produce optimal or near optimal solution. The experimental results are analyzed to check the performance of MA.

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Floorplanning Genetic Algorithm (ga) Local Search Memetic Algorithm (ma) Very Large Scale Integrated Circuit (vlsi) Ordered Tree (o-tree) Representation Depth First Search (dfs) Algorithm.