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Reseach Article

A Novel Approach for Multi-Bit Error Correction in Memories

Published on December 2013 by Jushwanth Xavier. X, Benujah. B. R
International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
Foundation of Computer Science USA
ICIIIOES - Number 11
December 2013
Authors: Jushwanth Xavier. X, Benujah. B. R
44e20ce6-c7b4-4226-bed9-18ef717b5f01

Jushwanth Xavier. X, Benujah. B. R . A Novel Approach for Multi-Bit Error Correction in Memories. International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences. ICIIIOES, 11 (December 2013), 1-4.

@article{
author = { Jushwanth Xavier. X, Benujah. B. R },
title = { A Novel Approach for Multi-Bit Error Correction in Memories },
journal = { International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences },
issue_date = { December 2013 },
volume = { ICIIIOES },
number = { 11 },
month = { December },
year = { 2013 },
issn = 0975-8887,
pages = { 1-4 },
numpages = 4,
url = { /proceedings/iciiioes/number11/14356-1314/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
%A Jushwanth Xavier. X
%A Benujah. B. R
%T A Novel Approach for Multi-Bit Error Correction in Memories
%J International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
%@ 0975-8887
%V ICIIIOES
%N 11
%P 1-4
%D 2013
%I International Journal of Computer Applications
Abstract

Due to advance technologies transistor size shrinks which makes the devices more vulnerable to noise and radiation effect. This affects the reliability of memories. Built-in current sensors (BICS) have been success in the case of single event upset (SEC). The process is taken one step further by proposing specific error correction codes to protect memories against multiple-bit upsets and to improve yield have been proposed. The method is evaluated using fault injection experiments. The results are compared with Hamming codes. The proposed codes provide a better performance compared to that of the hamming codes in terms of Single Event Upset. In the case of the Multi Bit Upset it provides better coverage in error deduction and correction.

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Index Terms

Computer Science
Information Sciences

Keywords

Multi-bit Error Correction Single Event Upset Hamming Codes.