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Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm

Published on December 2013 by Geo Niju Shanth, Saru Priya
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International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
Foundation of Computer Science USA
ICIIIOES - Number 1
December 2013
Authors: Geo Niju Shanth, Saru Priya
ea9f9e0e-2b44-4c40-94d5-f4af5e879f92

Geo Niju Shanth, Saru Priya . Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm. International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences. ICIIIOES, 1 (December 2013), 37-41.

@article{
author = { Geo Niju Shanth, Saru Priya },
title = { Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm },
journal = { International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences },
issue_date = { December 2013 },
volume = { ICIIIOES },
number = { 1 },
month = { December },
year = { 2013 },
issn = 0975-8887,
pages = { 37-41 },
numpages = 5,
url = { /proceedings/iciiioes/number1/14284-1367/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
%A Geo Niju Shanth
%A Saru Priya
%T Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm
%J International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
%@ 0975-8887
%V ICIIIOES
%N 1
%P 37-41
%D 2013
%I International Journal of Computer Applications
Abstract

This paper presents a resource efficient LDPC decoder architecture. The algorithm used for decoding LDPC is the min-sum algorithm. The decoder reduces the inter-connect complexity by restricting the extrinsic message length to 2 bits and also simplifies the check node operation. The algorithm is simulated and the results show that the performance is better than that of other algorithms. This algorithm can be incorporated into partially parallel hardware architecture to get significant savings in hardware resources when implemented in FPGA.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Error Correction Coding Ldpc Code Iterative Decoding Vlsi Design