A new method of achieving the target output with a less number of clock pulses has been introduced. Clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits. Although the word signal has a number of other meanings, the term here is used for "transmitted energy that can carry information". In some cases, more than one clock cycle is required to perform a predictable action. As the circuits become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult. A hierarchical low power module approach is utilized for near optimal results. A clock gating architecture can be added with the clock scheduling scheme to control the unnecessary power flow between the idle sequential circuits. The overall power reduction can be calculated by implementing the clock scheduling and power gating techniques in a SRAM Memory architecture with static and dynamic power calculation.

1. Tung-Hua Yeh and Sying Jyan Wang 2012 Power Aware High Level Synthesis with Gated Clock Skew Management.
2. Frans Theeuwen, Eric Seelen Power Reduction Through Clock gating by Symbolic Manipulation.
3. Li Li1, Jian Sun2, Yinghai Lu1, Hai Zhou1, Xuan Zeng2 "Low Power Discrete Voltage Assignment under Clock Skew Scheduling", Journal of Information Science and Engineering, 2009.
4. Shih-Hsu Huang, Chun-Hua Cheng and Dachen Tzeng Simultaneous Clock Skew Scheduling and Power Gated Module Selection for Standby Leakage Minimization.
5. Hariyama, M. , Ayoma, T. , and Kameyama, M. 2005. Genetic Approach to minimizing power consumption of VLSI Processors Using Multiple Supply Voltages.
6. Huang, S. H. , and Cheng, C. H. 2009 Timing Driven Power Gating in High Level Synthesis. " in Prof. Int. Conf. Comput. - Aided Des. Autom. Conf. , pp. 173-178.
7. Ni, M. , memik, S. O. , 2009. A Fast Heuristic Algorithm for Multidomain Clock Skew scheduling.
8. Obata, T. , Kaneko, M. , 2004 Clock Signal Skew Scheduling in RT Level Data path Synthesis.
9. Deokar, R. B. , Sapatnekar, S. S. 2007 A Graph Theoric Approach to Clock Skew Optimization.

Clock Skew Scheduling (css) Clock Skew Management High Level Synthesis (hls) Clock Gating.