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Design of Efficient Low Power Stable 4-Bit Memory Cell
| International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences |
| Foundation of Computer Science USA |
| ICIIIOES - Number 1 |
| December 2013 |
| Authors: K. Gavaskar, S. Priya |
| af04ef56-4a21-45cb-a534-f7c9e421e96d |
K. Gavaskar, S. Priya . Design of Efficient Low Power Stable 4-Bit Memory Cell. International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences. ICIIIOES, 1 (December 2013), 1-6.
Abstract
Memory is the most common part in CMOS IC's applications. The power consumption and speed of SRAMs are important issue that has led to multiple designs with the purpose of minimizing the power consumption during both read and write operations. In this paper, a novel 9T static random access memory (SRAM) cell design which consumes less dynamic power and has high read stability is predicted. This paper also includes the SRAM array structure, it consist of sense amplifier and address decoders. The Tanner EDA tool is used for observe the schematic solution at different technologies. Based on the results obtained when compared with the existing methods, by utilizing the above proposed method it is clearly observed that there is a decrease in power consumption and stability improvement of the memory cells.
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