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An Efficient System On-Chip Interconnect using Modified Smart Bias Circuit -2014

Published on November 2014 by Nithiya Devi.g, Sathiya Priya.j
International Conference on Innovations in Information, Embedded and Communication Systems
Foundation of Computer Science USA
ICIIECS - Number 2
November 2014
Authors: Nithiya Devi.g, Sathiya Priya.j
c6370ad8-d0a7-49e9-bc29-509eff178cd9

Nithiya Devi.g, Sathiya Priya.j . An Efficient System On-Chip Interconnect using Modified Smart Bias Circuit -2014. International Conference on Innovations in Information, Embedded and Communication Systems. ICIIECS, 2 (November 2014), 11-16.

@article{
author = { Nithiya Devi.g, Sathiya Priya.j },
title = { An Efficient System On-Chip Interconnect using Modified Smart Bias Circuit -2014 },
journal = { International Conference on Innovations in Information, Embedded and Communication Systems },
issue_date = { November 2014 },
volume = { ICIIECS },
number = { 2 },
month = { November },
year = { 2014 },
issn = 0975-8887,
pages = { 11-16 },
numpages = 6,
url = { /proceedings/iciiecs/number2/18656-1453/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Innovations in Information, Embedded and Communication Systems
%A Nithiya Devi.g
%A Sathiya Priya.j
%T An Efficient System On-Chip Interconnect using Modified Smart Bias Circuit -2014
%J International Conference on Innovations in Information, Embedded and Communication Systems
%@ 0975-8887
%V ICIIECS
%N 2
%P 11-16
%D 2014
%I International Journal of Computer Applications
Abstract

The most promising scheme for high-speed low power communication over long on-chip interconnects is Current-mode signaling (CMS) with dynamic overdriving scheme. A variation tolerant dynamic overdriving CMS scheme is proposed. The proposed CMS scheme employs a smart bias circuit in transmitter side. The smart bias is energy efficient and it reduces the delay. Current-mode signaling (CMS) scheme improves speed and reduces dynamic power consumption and it overcomes the drawback of voltage mode signaling. Although it consumes static power, it has a direct tradeoff between speed and static power. As the rise and fall delay is equal thereby it increases the throughput. However the voltage swing is decreased, the noise margin of data communication system get reduced. Dynamic over-driving is adopted for variation analysis which improves the energy, delay and EDP value over voltage mode signaling scheme.

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Index Terms

Computer Science
Information Sciences

Keywords

Current Mode Circuit Dynamic Over-driving On Chip-global Interconnects Modified Smart Bias.