CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
Reseach Article

Testable Sequential Circuits using Conservative Toffoli

Published on November 2014 by K.rekha Swathi Sri, M.mano, M.mohanaarasi
International Conference on Innovations in Information, Embedded and Communication Systems
Foundation of Computer Science USA
ICIIECS - Number 1
November 2014
Authors: K.rekha Swathi Sri, M.mano, M.mohanaarasi
35005890-bc06-4098-a428-8b1c037eaf81

K.rekha Swathi Sri, M.mano, M.mohanaarasi . Testable Sequential Circuits using Conservative Toffoli. International Conference on Innovations in Information, Embedded and Communication Systems. ICIIECS, 1 (November 2014), 34-38.

@article{
author = { K.rekha Swathi Sri, M.mano, M.mohanaarasi },
title = { Testable Sequential Circuits using Conservative Toffoli },
journal = { International Conference on Innovations in Information, Embedded and Communication Systems },
issue_date = { November 2014 },
volume = { ICIIECS },
number = { 1 },
month = { November },
year = { 2014 },
issn = 0975-8887,
pages = { 34-38 },
numpages = 5,
url = { /proceedings/iciiecs/number1/18652-1443/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Innovations in Information, Embedded and Communication Systems
%A K.rekha Swathi Sri
%A M.mano
%A M.mohanaarasi
%T Testable Sequential Circuits using Conservative Toffoli
%J International Conference on Innovations in Information, Embedded and Communication Systems
%@ 0975-8887
%V ICIIECS
%N 1
%P 34-38
%D 2014
%I International Journal of Computer Applications
Abstract

Testing of Sequential circuits can be done by two test vectors (all 1's and all 0's) if the circuits were based on the conservative logic. The circuit is made to be tested by designing the circuit with the help of Reversible logic gates. Toffoli gate is used as reversible gate in this paper. Sequential circuits such as latches, flip flops are designed with the help of conservative logic reversible gate. Therefore, testing does not require any scan path access to the internal memory cell since only normal mode and test mode are required for testing. Equivalent circuit of the Toffoli gate is presented which achieves the fault coverage. The objective of this paper is to reduce the number of test vectors. Fault coverage is also achieved rather than designing the circuit with fredkin gate. Power consumption may also reduce when compared with the fredkin gate.

References
  1. E. Fredkin and T. Toffoli, "Conservative logic," Int. J. Theor. Phys. ,vol. 21, nos. 3–4, pp. 219–253, 1982.
  2. Himanshu Thapliyal and Saurabh Kotiyal,"Design of testable reversible sequential circuits", IEEE Transaction on very large scale integration systems. , vol. 21, no. 7, july 2013.
  3. sk. noor mahammad and kamakoti veezhinathan ," constructing online testable circuitsusing reversible logic, IEEE transactions on instrumentation and measurement, vol. 59, no. 1, january 2010.
  4. H. Thapliyal and N. Ranganathan, "Design of reversible sequential circuits optimizing quantum cost, delay and garbage outputs," acm j. emerg. technol. comput. syst. , vol. 6, no. 4, pp. 14:1–14:35, dec. 2010.
  5. Himanshu Thapliyal and Nagarajan Ranganathan," design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs"
  6. Jie Ren and Vasili K. Semenov,progress with physically and logically reversible superconducting digital circuits, IEEE transactions on applied superconductivity, vol. 21, no. 3, june 2011
  7. Design, synthesis and test of reversible circuits for emerging nanotechnologies, vlsi (isvlsi), 2012 ieee computer society annual symposium.
  8. M. Hasan, A. Islam, and A. Chowdhury, "Design and analysis of online testability of reversible sequential circuits," in Proc. Int. Conf. Comput. Inf. Technol. , Dec. 2009, pp. 180–185.
  9. M. Pedram, Q. Wu, and X. Wu, "A new design for double edge triggeredflip-flops," in Proc. Asia South Pacific Design Autom. Conf. , 1998, pp. 417–421.
  10. H. Thapliyal, M. B. Srinivas, and M. Zwolinski, "A beginning in the reversible logic synthesis of sequential circuits," in Proc. Int. Conf.
  11. Military Aerosp. Program. Logic Devices, Washington, DC, Sep. 2005, pp. 1–5.
  12. P. Kartschoke, "Implementation issues in conservative logic networks," M. S. thesis, Dept. Electr. Eng. , Univ. Virginia, Charlottesville, 1992.
  13. J. Ren and V. K. Semenov, "Progress with physically and logically reversible superconducting digital circuits," IEEE Trans. Appl. Superconduct. , vol. 21, no. 3, pp. 780–786, Jun. 2011.
  14. Md. Saiful Islam, "A Novel Quantum cost efficient reversible full adder in nanotechnology".
  15. Prashant. R. Yelekar, Prof. Sujata S. Chiwande "Introducton to reversible logic gates and its application" in National Conf, 2011.
  16. Sujata S. Chiwande, Shipa S. Katre, Sushmita S. Dalvi, Jyoti C Kolte, "Performance analysis of sequential circuits using reversible logic", Int journal, vol. 2,Issue 1 ,Jan 2013.
  17. Raghava Garipelly, P. Madhu kiran, A. Santhosh "A review on reversible logic gates and its implementation",Int Journal,vol. 3, Issue 3, Mar 2013.
  18. Himanshu Thapliyal, Nagarajan ranganathan,"Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs".
Index Terms

Computer Science
Information Sciences

Keywords

Conservative Logic Reversible Gate Fredkin Gate Toffoli Gate.