In a Core based SoC design various Intellectual Property (IP) cores are integrated on a single chip called System on chip(SoC). The testing of this SoC is complex, resulting in a long test application time. But the testing time cannot be too long as the relevant cost will increase rapidly. The testing time can be minimized if an effective scheduling of the tests is done. This paper presents a test scheduling scheme for a core based SoC. The SoC test scheduling is an NP complete problem and hence this paper presents Genetic algorithm based test scheduling scheme for a core based SoC so as to minimize the testing time incorporating the power dissipation constraints. Genetic algorithm generate solutions to the scheduling problem using techniques inspired by natural evolution. The optimal solution obtained by running genetic algorithm is applied to the ITC'02 SoC test Benchmarks and provides minimum test time results.

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Core Based Soc Test Scheduling Test Application Time Soc Test Benchmarks.