A processor devotes a considerable amount of processing time in performing arithmetic operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than other arithmetic operations. So, Multiplier is one of the most important arithmetic units in processors and also a major source of power dissipation. Reducing the power dissipation, limiting the processing time and transistor count of multipliers are the key factors for designing various digital circuits and systems. To achieve high execution speed, parallel array multipliers are widely used. But these multipliers consume more power. The fundamental units to design a multiplier are adders. Additions are required to be performed using low- power, area-efficient circuits operating at greater speed. This paper aims at analyzing the power dissipation, circuit delay and finally PDP(Power-Delay Product) of parallel array multipliers by using only low power N-MOS based 1-bit full adder. The design has been done using DSCH 2. 6c and simulated using 0. 18um CMOS technology at 2. 5V supply with MICROWIND 2. 6a. Comparison of the results of post layout analysis with similar previous multiplier circuits proves efficiency of the proposed multiplier.

1. A. M. Shams and M. Bayoumi, "A novel high-performance CMOS1-bit full adder cell," IEEETransaction on Circuits Systems II, Analog Digital Signal Process, vol. 47, no. 5, pp. 478–481, May2000.
2. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design,A System Perspective, Addison- Wesley, 1993
3. N. Zhuang and H. Wu, "A new design of the CMOS full adder," IEEE J. Solid-State Circuits, vol. 27, no. 5, pp. 840–844, May 1992.
4. R. Shalem, E. John, and L. K. John, "A novel low-power energy recovery full adder cell," in Proc. Great Lakes Symposium on VLSI, pp. 380–383, Feb. 1999.
5. S. Goel. A. Kumar, M. A. Bayoumi, "Design of robust, energy –efficient full adders for deep sub micrometer design using hybrid-CMOS logic style," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1309-1321, Dec. 2006.
6. Zhang, M. , J. Gu and C. H. Chang, "A novel hybrid pass logic with static CMOS output drive full adder cell," IEEE Int. Symposium on Circuits Systems, vol. 5, pp. 317-320, May 2003.
7. Manoj Kumar, Sandeep K. Arya and SujataPandey ,"Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate", International Journal of VLSI design & Communication Systems (VLSICS) Vol. 2, No. 4, December 2011
8. T. DivyaBharathi, B. N. SrinivasaRao, "Design and Implementation of Low-Power High- Speed Full Adder cell using GDI Technique", International Journal of Engineering Science and Innovative Technology (IJESIT) Volume 2, Issue 2, March 2013
9. Kudithipudi, Dhireesha, and Eugene John. "Implementation of low power digital multipliers using 10 transistor adder blocks. " Journal of Low Power Electronics1. 3 (2005): 286-296.
10. Damle, M. B. , Dr SS Limaye, and M. G. Sonwani. "Comparative Analysis of Array Multiplier Using Different Logic Styles. " IOSR Journal of Engineering (IOSRJEN) 3. 5 (2013): 16-22.
11. SrinivasaRao, Janagam, and Gulivindala Suresh. "Performance Analysis of Full Adder & It's Impact on Multiplier Design. " International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-3, Issue-4, September 2013
12. Sharma, Abhay. "FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase. " International Journal of Computer Applications 116. 17 (2015).
13. Ravi, N. , Satish, A. , Prasad, T. J. , & Rao, T. S. (2011). A New Design for Array Multiplier with Trade off in Power and Area. arXiv preprint arXiv:1111. 7258.
14. Bansal, Himanshu, K. G. Sharma, and Tripti Sharma. "Wallace Tree Multiplier Designs: A Performance Comparison Review. " Innovative Systems Design and Engineering 5. 5 (2014): 60-67.
15. Debanjana Datta and Debarshi Datta, "A Novel Power Efficient N-MOS Based 1-Bit Full Adder", IEEE International Conference on Microelectronics, Computing and Communication (MicroCom 2016).

Pdp c-mos N-mos Delay Power Multiplier Adder