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Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning

Published on September 2016 by Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar
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International Conference on Emerging Trends in Informatics and Communication
Foundation of Computer Science USA
ICETIC2016 - Number 1
September 2016
Authors: Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar
dcdd6fd9-22b8-4df7-856e-e440c64be297

Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar . Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning. International Conference on Emerging Trends in Informatics and Communication. ICETIC2016, 1 (September 2016), 23-27.

@article{
author = { Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar },
title = { Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning },
journal = { International Conference on Emerging Trends in Informatics and Communication },
issue_date = { September 2016 },
volume = { ICETIC2016 },
number = { 1 },
month = { September },
year = { 2016 },
issn = 0975-8887,
pages = { 23-27 },
numpages = 5,
url = { /proceedings/icetic2016/number1/25871-4010/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Emerging Trends in Informatics and Communication
%A Mamata Panigrahy
%A Indrajit Chakrabarti
%A Anindya Sundar Dhar
%T Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning
%J International Conference on Emerging Trends in Informatics and Communication
%@ 0975-8887
%V ICETIC2016
%N 1
%P 23-27
%D 2016
%I International Journal of Computer Applications
Abstract

This paper presents the hardware architecture for fractal image compression (FIC) with quadtree partitioning. Fractal image coding with quadtree partitioning allows one to produce higher quality of image. Processing image areas of different complexity with image blocks of varying size enables proper exploration of image details. Additionally, exploiting parallelism present within the algorithm and adopting hardware based solutions speed up the encoding process. The proposed architecture has been implemented on Xilinx Vertex-5 FPGA operating at a frequency of 154MHz.

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Index Terms

Computer Science
Information Sciences

Keywords

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