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Asynchronous Router for Network-on-Chip on FPGA

Published on September 2015 by Gauri Suresh Bhosale, Arati S. Phadke
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CAE Proceedings on International Conference on Communication Technology
Foundation of Computer Science USA
ICCT2015 - Number 1
September 2015
Authors: Gauri Suresh Bhosale, Arati S. Phadke
c7db2338-a43e-40df-a1a8-f27d72558d1c

Gauri Suresh Bhosale, Arati S. Phadke . Asynchronous Router for Network-on-Chip on FPGA. CAE Proceedings on International Conference on Communication Technology. ICCT2015, 1 (September 2015), 1-5.

@article{
author = { Gauri Suresh Bhosale, Arati S. Phadke },
title = { Asynchronous Router for Network-on-Chip on FPGA },
journal = { CAE Proceedings on International Conference on Communication Technology },
issue_date = { September 2015 },
volume = { ICCT2015 },
number = { 1 },
month = { September },
year = { 2015 },
issn = 0975-8887,
pages = { 1-5 },
numpages = 5,
url = { /proceedings/icct2015/number1/22630-1530/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 CAE Proceedings on International Conference on Communication Technology
%A Gauri Suresh Bhosale
%A Arati S. Phadke
%T Asynchronous Router for Network-on-Chip on FPGA
%J CAE Proceedings on International Conference on Communication Technology
%@ 0975-8887
%V ICCT2015
%N 1
%P 1-5
%D 2015
%I International Journal of Computer Applications
Abstract

In Network-on-chip router is the main block where one of the major decisions about the route direction is taken. This paper presents asynchronous router implemented using handshaking signals. Distributed routing with 3X3 Mesh topology is used in this design. 2D Mesh is the most common topologies due to its grid-type shape and regular structure which is most appropriate for the two dimensional layout on a chip. The design is synthesized for the Stratix II EP2S15F484C3 FPGA using Quartus II software. The router supports maximum of five simultaneous routing requests.

References
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  8. Chawade, S. D. , Gaikwad, M. A. , & Patrikar, R. M. (2012). Review of XY Routing Algorithm for Network-On-Chip Architecture. International Journal of Computer Applications, 43(21).
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Index Terms

Computer Science
Information Sciences

Keywords

Network On Chip Wormhole Switching Xy Routing Algorithm Asynchronous Router