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FPGA Implementation of Viterbi Decoder

Published on March 2012 by Anubhuti Khare, Manish Saxena, Jaagdish Patel
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International Conference in Computational Intelligence
Foundation of Computer Science USA
ICCIA - Number 1
March 2012
Authors: Anubhuti Khare, Manish Saxena, Jaagdish Patel
415cdfb7-048f-4a05-aaa2-1196a3b16fda

Anubhuti Khare, Manish Saxena, Jaagdish Patel . FPGA Implementation of Viterbi Decoder. International Conference in Computational Intelligence. ICCIA, 1 (March 2012), 36-40.

@article{
author = { Anubhuti Khare, Manish Saxena, Jaagdish Patel },
title = { FPGA Implementation of Viterbi Decoder },
journal = { International Conference in Computational Intelligence },
issue_date = { March 2012 },
volume = { ICCIA },
number = { 1 },
month = { March },
year = { 2012 },
issn = 0975-8887,
pages = { 36-40 },
numpages = 5,
url = { /proceedings/iccia/number1/5096-1008/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference in Computational Intelligence
%A Anubhuti Khare
%A Manish Saxena
%A Jaagdish Patel
%T FPGA Implementation of Viterbi Decoder
%J International Conference in Computational Intelligence
%@ 0975-8887
%V ICCIA
%N 1
%P 36-40
%D 2012
%I International Journal of Computer Applications
Abstract

The main goal of this paper was resource-optimized implementation of the decoder on the target platform. It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. In this paper, we present a Spartan XC3S400A field-programmable gate array implementation of Viterbi Decoder with a constraint length of 3 and a code rate of 1/3. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309.

References
  1. M. Boo F. Arguello, JD Bruguera, R. Doallo, and EL Zapata. “High-performance VLSI architecture for the Viterbi Algorithm”, IEEE transactions on communications, 45(2): p.p.168–176, 2011.
  2. Inyup Kang, Member IEEE and Alan N. Wilson (1998). “Low Power Viterbi Decoder for CDMA Mobile Terminal”, IEEE Journal of Solid State Circuits. IEEE. Vol 33. p.p. 473-481, 2010.
  3. D.J.Muder,”Minimal trellises for Block codes,”IEEE Transaction Information Theory, Vol34, p.p.1049- 1053, Se2009.
  4. Miloš Pilipovic, Marija Tadic, “FPGA Implementation of Soft Input Viterbi Decoder for CDMA2000 System”, 16th Telecommunications forum TELFOR 2008.
  5. Iakovos Mavroidis, “FPGA Implementation of the Viterbi Decoder”, University of California Berkeley, Dec. 1999.
  6. Hema.S, Suresh Babu.V, Ramesh P, “FPGA Implementation of Viterbi Decoder”, 6th WSEAS Int. Conf. on Electronics, February 2007.
  7. A. J. Viterbi, “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Trans. Inform. Theory, vol. IT-13, pp. 260-269, Apr. 1967.
  8. John G. Proakis (2001). “Digital Communication”. McGraw Hill, Singapore. pp 502-507, 471-475, 2010.
  9. Viterbi, A.”Convolutional codes and their performance in communication systems “IEEE Trans. Commun. Technol” ,VOl .Com 19, no ,5, Oct.1971, pp.715-772, 2009.
Index Terms

Computer Science
Information Sciences

Keywords

Convolutional encoder Viterbi decoder FPGA Spartan XC3S400A FPGA FEC (Forward Error Correction) Path memory Register Exchange