CFP last date
22 April 2024
Reseach Article

High Performance DCT Implementation using NEDA on FPGA

Published on March 2012 by Monika Zope, P. S. Mahajani
International Conference in Computational Intelligence
Foundation of Computer Science USA
ICCIA - Number 1
March 2012
Authors: Monika Zope, P. S. Mahajani
f446b45c-560d-48f9-a6c5-02be6671053c

Monika Zope, P. S. Mahajani . High Performance DCT Implementation using NEDA on FPGA. International Conference in Computational Intelligence. ICCIA, 1 (March 2012), 6-10.

@article{
author = { Monika Zope, P. S. Mahajani },
title = { High Performance DCT Implementation using NEDA on FPGA },
journal = { International Conference in Computational Intelligence },
issue_date = { March 2012 },
volume = { ICCIA },
number = { 1 },
month = { March },
year = { 2012 },
issn = 0975-8887,
pages = { 6-10 },
numpages = 5,
url = { /proceedings/iccia/number1/5090-1002/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference in Computational Intelligence
%A Monika Zope
%A P. S. Mahajani
%T High Performance DCT Implementation using NEDA on FPGA
%J International Conference in Computational Intelligence
%@ 0975-8887
%V ICCIA
%N 1
%P 6-10
%D 2012
%I International Journal of Computer Applications
Abstract

DCT is at the core of the most current generation of image and video compression standards including JPEG, H.261, H.263+, MPEG-1, 2, 4. Distributed arithmetic approach increases the speed and accuracy while reducing cost metrics, power and area of the DSP applications. As reducing cost is attracting more and more attention in application-specific integrated circuit design, there is an increasing demand for more efficient DA paradigms which can eliminate the need of using ROMs. At the same time, it is capable of meeting throughput constraints. To meet this demand New Distributed Arithmetic (NEDA) approach is introduced. NEDA features implementation without the need of multipliers as in conventional MAC approach, and at the same time, without the need of ROM as in DA approach. NEDA can also expose redundancy existing in the adder array consisting of entries of 0 and 1. VHDL code for calculation of DCT is written and this code is synthesized and simulated. The simulation results are verified by comparing with MATLAB results.

References
  1. Ahmed M. Shams, Archana Chidanandan, Wendi Pan,Magdy A. Bayoumi, “ NEDA: A Low-Power High-Performance DCT Architecture”, IEEE Trans. On Signal Processing, VOL. 54, NO. 3, pp.955-964, March 2006
  2. Ahmed M. Shams, Archana Chidanandan,, Wendi Pan,Magdy A. Bayoumi, “A Low-Power High-Performance Distributed Architecture”, IEEE Trans. On Signal Processing,VOL.40,NO.3,pp.415-420, Dec.2002
  3. S. Yu, E.E. Swartzlander Jr., “DCT Implementation with Distributed Arithmetic," IEEE Transactions on Computers, vol.50, pp.985-991, Sept. 2001
  4. August, N.J., Dong Sam Ha, “Low power design of DCT and IDCT for low bit rate video codecs”, IEEE Trans. Multimedia, Vol. 6, pp. 414-422, June 2004
  5. Iain E.G. Richardson, “Video Codec Design-Developing Image and Video Compression Systems”, John Willy and Sons, LTD, pp.138-148,2002.
  6. V. Bhaskaran, K. Konstantinides, “Image and Video Compression Standerds”, Kluwer academic publishers,pp.74-95,1995
Index Terms

Computer Science
Information Sciences

Keywords

DCT Distributed Arithmetic ASIC NEDA Compression standards