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HDL Implementation of Digital Image Display on VGA through FPGA
| International Conference on Advances in Emerging Technology |
| Foundation of Computer Science USA |
| ICAET2017 - Number 5 |
| July 2018 |
| Authors: Rohit Raj, Gaurav Mittal, Monika Aggarwal |
| 4a627cc2-c723-4564-81b1-38b90e91da75 |
Rohit Raj, Gaurav Mittal, Monika Aggarwal . HDL Implementation of Digital Image Display on VGA through FPGA. International Conference on Advances in Emerging Technology. ICAET2017, 5 (July 2018), 14-19.
Abstract
For rigorous computer vision applications for image processing on embedded platforms is still a very challenging task. For a customized hardware Field-programmable gate arrays (FPGAs) offer a suitable technology to accelerate image processing. Most recent available image processing frameworks are concentrated on pixel-based modules for simple preprocessing tasks which are mainly defined using MATLAB. This presented paper deals with the aims to implementation of image/digital data into real time hardware using HDLs with the motto of relatively inexpensive and adaptable technology. Thus, it offers modules and interfaces to perform operations and incorporate software defined operations. This paper will show to how the digital image (of any source/formats) can be stored into a memory(RAM/ROM) onto the FPGA and how it can be further processed for larger display onto the TV (i. e. VGA).
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