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BIST Design For Static Neighbourhood Pattern Sensitive Fault Test

Published on June 2013 by Anu Samanta, Mousumi Saha, Ajay Kumar Mahato
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International Conference on Communication, Circuits and Systems 2012
Foundation of Computer Science USA
IC3S - Number 5
June 2013
Authors: Anu Samanta, Mousumi Saha, Ajay Kumar Mahato
d4db8fd0-a2a2-4cd8-8548-82a446601ff6

Anu Samanta, Mousumi Saha, Ajay Kumar Mahato . BIST Design For Static Neighbourhood Pattern Sensitive Fault Test. International Conference on Communication, Circuits and Systems 2012. IC3S, 5 (June 2013), 23-28.

@article{
author = { Anu Samanta, Mousumi Saha, Ajay Kumar Mahato },
title = { BIST Design For Static Neighbourhood Pattern Sensitive Fault Test },
journal = { International Conference on Communication, Circuits and Systems 2012 },
issue_date = { June 2013 },
volume = { IC3S },
number = { 5 },
month = { June },
year = { 2013 },
issn = 0975-8887,
pages = { 23-28 },
numpages = 6,
url = { /proceedings/ic3s/number5/12314-1364/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Communication, Circuits and Systems 2012
%A Anu Samanta
%A Mousumi Saha
%A Ajay Kumar Mahato
%T BIST Design For Static Neighbourhood Pattern Sensitive Fault Test
%J International Conference on Communication, Circuits and Systems 2012
%@ 0975-8887
%V IC3S
%N 5
%P 23-28
%D 2013
%I International Journal of Computer Applications
Abstract

[1] A. J. VAN DE GOOR and C. A. VERRUIJT. "An Overview of Deterministic Functional RAM Chip Testing". ACM Computing Surveys, Vol. 22, No. 1, March 1990. [2] V. D. A. Michael Lee Bushnell, Vishwani D. Agrawal, "Essentials of Electronic Testing for Digital, Memory, and Mixed -Signal VLSI Circuits". New York: Kluwer Academic Publishers, 2nd ed. , 2002 [3] Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji and Arun N. Chandorkar. "Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories" Proceedings of the 17 th International Conference on VLSI Design (VLSID 04) 1063-9667/04 $ 20. 00@2004 IEEE. [4] Allen C. Cheng. "Comprehensive Study in Designing Memory BIST Algorithms, Implementations and Trade offs" EECS 579, Fall 2002 Digital System Testing. [5] S. Wolfram, "Cellular Automata and Complexity," collected papers, pp. 1-25, 1994. [6] M. A. Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman, "Digital Systems Testing and Testable Design"Jaico Publishing House, 2002.

References
  1. A. J. VAN DE GOOR and C. A. VERRUIJT. "An Overview of Deterministic Functional RAM Chip Testing". ACM Computing Surveys, Vol. 22, No. 1, March 1990.
  2. V. D. A. Michael Lee Bushnell, Vishwani D. Agrawal, "Essentials of Electronic Testing for Digital, Memory, and Mixed -Signal VLSI Circuits". New York: Kluwer Academic Publishers, 2nd ed. , 2002
  3. Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji and Arun N. Chandorkar. "Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories" Proceedings of the 17 th International Conference on VLSI Design (VLSID 04) 1063-9667/04 $ 20. 00@2004 IEEE.
  4. Allen C. Cheng. "Comprehensive Study in Designing Memory BIST Algorithms, Implementations and Trade offs" EECS 579, Fall 2002 Digital System Testing.
  5. S. Wolfram, "Cellular Automata and Complexity," collected papers, pp. 1-25, 1994.
  6. M. A. Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman, "Digital Systems Testing and Testable Design"Jaico Publishing House, 2002.
Index Terms

Computer Science
Information Sciences

Keywords

BIST Design