Hybrid SET-CMOS circuits which combine the merits of both the SET [Single Electron Transistor] and CMOS promises to be a practical implementation for future low power ultra-dense VLSI/ULSI circuit design. In this work, an SET-CMOS hybrid hysteresis circuit is proposed. The MIB model for SET and BSIM4 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment.

1. Bingcai Sui, Liang Fang, Yaqing Chi, and Chao Zhang, "Nano-Reconfigurable Cells With Hybrid Circuits of Single-Electron Transistors and MOSFETs," IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 9, SEPTEMBER 2010,pp. 2251-2257.
2. Santanu Mahapatra, Adrian Mihai Ionescu, " Hybrid CMOS Single-Electron-Transistor Device and Circuit Design" Artech House, Inc. ,ISBN:1596930691,2006. R
3. Anindya Jana, Rajat Suvra Halder, J. K. Sing, Subir Kumar Sarkar,"Design and simulation of hybrid SET CMOS based sequential circuits", Journal of Nano and Electronic Physics, Vol. 4 No. 2,02004(5pp)(2012).
4. Uchida, K. , et al. , "Programmable Single-Electron Transistor Logic for Low-Power Intelligent Si LSI," Proc. of. ISSCC 2002, Vol. 2, pp. 162– 453. Spector, A. Z. 1989. Achieving application requirements. In Distributed Systems, S. Mullender
5. C. Lageweg, S. Cotofana, and S. Vassilidis, "Single Electron Encoded Latches and Flip- flops," IEEE Trans. On Nanotechnology, vol. 3, no. 2 (2004).

Single Electron Transistor Cmos Hybrid Cmos-set Circuits Mib T-spice